1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and to a method of generating different voltages, and in particular, to a semiconductor integrated circuit which generates a boosted voltage and which generates a converted voltage based on the boosted voltage in order to activate a liquid crystal panel, and to a method of generating the boosted voltage and the converted voltage. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-307333 filed on Oct. 21, 2004, which is herein incorporated by reference.
2. Description of the Related Art
FIG. 1 is a circuit block diagram for describing a semiconductor integrated circuit which generates different voltages in the related art. As shown in FIG. 1, the semiconductor integrated circuit of the related art includes a control circuit 610, a boost circuit 620 and a step-down circuit 630. The boost circuit 620 generates a boosted voltage VDD based on a first external power supply voltage VCC1 in accordance with a control signal which is generated from the control circuit 610 based on a second external power supply voltage VCC2. On the other hand, the step-down circuit 630 generates a step-down voltage VEE based only on the boosted voltage VDD which is output from the boost circuit 620. The above-described semiconductor integrated circuit is described in a Patent Document 1 (Japanese Patent Publication Laid-open No. 2003-91268).
However, since the step-down circuit 630 generates the step-down voltage VEE based only on the boosted voltage VDD which is output from the boost circuit 620, electrical charge in the boosted voltage VDD may be consumed. Therefore, the boosted voltage VDD may be decreased. On such an occasion, a plurality of parasitic bipolar transistors 710 and 720 may appear in a semiconductor substrate 600 on which the boost circuit 620 and the step-down circuit 630 are disposed as shown in FIG. 2.
FIG. 2 is a sectional view for describing the semiconductor substrate 600 in which the parasitic bipolar transistors 710 and 720 appear. As shown in FIG. 2, the semiconductor substrate has a P-type conductivity and further includes a PMOS transistor Tr1 which configures the boosted circuit 620, and an NMOS transistor Tr2 which configures the step-down circuit 630. The PMOS transistor Tr1 is disposed on an N-conductive type well which is arranged in the semiconductor substrate 600, and the NMOS transistor Tr2 is disposed on the semiconductor substrate 600. When the boosted voltage VDD is decreased, the parasitic bipolar transistors 710 and 720 appear between the PMOS transistor Tr1 of the boosted circuit 620 and the NMOS transistor Tr2 of the step-down circuit 630. That is, a collector current passes through the parasitic bipolar transistor 710, and then an electrical potential is increased in accordance with the collector current of the parasitic bipolar transistor 710. Therefore, the parasitic bipolar transistor 720 is turned ON. As a result, a thyristor configured with the parasitic bipolar transistors 710 and 720 is turned ON, and a latch-up phenomenon may appear between the PMOS transistor Tr1 of the boosted circuit 620 and the NMOS transistor Tr2 of the step-down circuit 630. In order to suppress the latch-up phenomenon in the semiconductor substrate 600, a diode may be coupled to an output terminal of the boosted circuit 620 outside the boosted circuit 620 and the step-down circuit 630. However, formation of the diode increases cost and further complicates the manufacturing processes.